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Integrated Circuit Systems, Inc.
ICS9222-01
Dual Memory Clock Generator
General Description
The ICS9222-01 is a High-speed clock generator providing two channels up to 450 MHz differential clock source for direct Rambus_memory system. It includes two independent DDLL's (Distributed Delay locked loop) and phase detection mechanisms to synchronize eachdirect Rambus_ channel clock to an external system clock. ICS9222-01 provides a solution for a broad range of Direct Rambus memory applications. The device works in conjunction with the ICS964S101, as well as 9250-22 and others (depending on chipset). The ICS9222-01 power management support system turns "off" the Rambus channel clock to minimize power consumption for mobile and other power sensitive applications. In "clock off" mode the device remains "on" while the output is disabled, allowing fast transitions between clock-off and clock-on states. In "power down" mode it completely powers down for minimum power dissipation.
Features
* * * * * Compatible with all Direct RambusTM based ICs Up to 450 MHz differential clock source for direct RambusTM memory system Cycle to cycle jitter is less than 100 ps 3.3 5% supply Synchronization flexibility: Supports systems that need clock domains of Rambus channel to synchronize with system or processor clock, or systems that do not require synchronization of the Rambus clock to another system clock. Excellent power management support REFCLK input is from the main clock generator such as a 9250-22.
* *
Block Diagram
CLK_STOP# PD# FS (2:0) GND PLLclk PCLK1 SYNCLK1
Pin Configuration
VDDREF REFCLK VDDC SYNCLK0 PCLK0 GND VDDP GND SYNCLK1 PCLK1 VDDC VDDIPD CLK_STOP# PD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 FS0 FS1 FS2 GND CLKB0 CLK0 VDDCLK VDDCLK CLK1 CLKB1 GND MULT_0 MULT_1 MULT_2
Test MUX
Bypass MUX
Bypclk
Phase Detector Phase Aligner
REFCLK B A MULT (2:0) 2 GND CLK1 CLKB1
PLL Phase Aligner Phase Detector
GND PAclk
CLK0 CLKB0
28-Pin TSSOP
PCLK0 SYNCLK0
0274B--04/08/02
ICS9222-01
ICS9222-01
Pin Descriptions
Pin #
1, 7, 21, 22 2 3, 11 6, 8, 18, 25 4, 5, 9, 10 12 13 14 15, 16, 17 19, 24 20, 23 26, 27, 28
Name
VDD REFCLK VDDC GND PCLK, SYNCLK VDDIPD CLK_ STOP# PD# MULT (2:0) CLKB (1:0) CLK (1:0) FS (2:0)
Type
PW R IN PW R PW R IN PW R IN IN IN OUT OUT IN
Description
3.3 V power supply Reference clock Power for phase aligners Ground Phase controller input, used to drive a phase aligner that adjusts the phase of the busclk. Voltage for phase detector inputs Active low output enable/disable for CLK/CLKB 3.3V CMOS active low power down, the device is powered down when the "(PD#) =0" 3.3V CMOS PLL Multiplier select, logic for selecting the multiply ratio for the PLL from the input REFCLK Clock output Complement Clock output 3.3V CMOS Mode control, used in selecting bypass, test, normal, and output test (OE)
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ICS9222-01
PLL Divider Selection and PLL Values (PLLCLK=REFCLK*A/B)
CLK(1:0)/CL KB(1:0) w/ REFCLK= 50MHz Reserved Reserved 300 450 Reserved Reserved 400 Reserved CLK(1:0)/CL KB(1:0) w/ REFCLK= 66MHz 267M Hz 300 400 Reserved Reserved 356 Reserved Reserved
MULT_0 MULT_1 MULT_2
A
B
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
4 9 6 9 8 16 8 10
1 2 1 1 3 3 1 1
Bypass and Test Mode Select
FS0 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS2 0 1 0 1 0 1 0 1 MODE Normal Supplier Test OE OE B ypass Supplier Test Test Reserved CLK (1:0) C LK R eserved Tristate Tristate No n-aligned C LK R eserved R EFC LK R eserved CLKB (1:0) C LKB R eserved Tristate Tristate Non-aligned CLKB R eserved R EFC LKB R eserved
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ICS9222-01
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Outputs
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated) PARAMETER Supply Voltage REFCLK Input cycle time Input Cycle-to-Cycle Jitter Input Duty Cycle over 10K cycles Input frequency of modulation Modulation index Phase detector input cycle time at PCLK (1:0) & SYNCLK (1:0) Initial phase error at phase detector inputs Phase detector input duty cycle over 10K cycles Input rise & fall times (measured at 20%-80% of input voltage) for PCLK (1:0), SYNCLK (1:0) & REFCLK Input capacitance at PCLK (1:0) & SYNCLK (1:0) & REFCLK Input capacitance matching at PCLK (1:0) & SYNCLK (1:0) Input capacitance at CMOS pins Input (CMOS) signal low voltage Input (CMOS) signal high voltage REFCLK input low voltage REFCLK input high voltage Input signal low voltage for PD inputs and STOP_CLK Input signal high voltage for PD inputs and STOP_CLK Input supply reference for REFCLK Input supply reference for PD inputs Phase detector phase error for distributed loop measured at PCLK (1:0) & SYNCLK (1:0) Clock Cycle time Cycle-to-cycle jitter at CLK (1:0) & CLKB (1:0) Total jitter over 2 ,3 or 4 cycles Phase aligner phase step size CLK (1:0) & CLKB (1:0) PLL output phase error when tracking SSC Output crossing-point voltage Output voltage during Clk Stop (CLK_STOP#=0) Output Voltage swing Output low voltage Output high voltage Output duty cycle over 10K cycles Output cycle-to-cycle duty cycle error Output rise & fall times (measured at 20%-80% of input voltage) for PCLK (1:0), SYNCLK (1:0) & REFCLK Difference between rise and fall times on a single device (20%-80%) Operating Supply Current 400MHz SYMBOL VDD tCYCLE,IN tJ,IN DCIN FM,IN PM,IN tCYCLE,PD terr,init DCIN,PD tIR, tIF CIN,PD CIN,PD CIN,CMOS VIL VIH VIL,R VIH,R VIL,R VIH,R VDD,IR VDD,IPD tERR,PD tCYCLE tJ tJ tSTEP tERR,SSC VX VX,STOP VCOS VOL VOH DC tDC,ERR tCR,tCF tCR,CF MIN 3.135 10 40% 30 0.25 30 -0.5 25% 0.7 0.7 0.7 1.235 1.235 -100 2.5 1 -100 1.3 1.1 0.4 1 40% 300 MAX 3.465 40 250 60% 33 0.5 100 0.5 75% 1 7 0.5 10 0.3 0.3 0.3 3.465 3.465 100 3.75 60 100 100 1.8 2 1 2.35 60% 50 500 100 250 UNIT V ns ps tCYCLE kHz % ns t CYCLE,PD t CYCLE,PD ns pF pF pF VDD VDD VDD,IR VDD,IR VDD,IPD VDD,IPD V V ps ns ps ps ps ps V V V V V tCYCLE ps ps ps mA
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ICS9222-01
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D SEE VARIATIONS E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS 0 8 aaa -0.10 VARIATIONS N 28 D mm. MIN 9.60 MAX 9.80
In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
-Ce
b SEATING PLANE
D (inch) MIN .378 MAX .386
aaa C
Reference Doc.: JEDEC Publication 95, MO-153 10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil)
Ordering Information
ICS9222yG-01-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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